Lead ASIC Verification Architect – Systems & Methodologies

A leading photonics company in San Jose is seeking a Principal Design Verification Engineer to lead the verification strategy for advanced silicon photonic chips. In this pivotal role, you will architect scalable verification environments and drive high-quality silicon from concept to production. Ideal candidates will possess an MS in Electrical Engineering, 12+ years of relevant experience, and expertise in SystemVerilog and UVM. This position offers a salary range of $180,000 to $230,000. #J-18808-Ljbffr