Infineon Technologies
Staff Engineer Digital Signal Processing
Infineon Technologies, San Jose, California, United States, 95199
Staff Engineer Digital Signal Processing
As a Staff Engineer Digital Signal Processing on our Research & Development team, you'll merge creativity with your technical expertise to shape the future of technology, drive groundbreaking projects, and bring new ideas to life.
Your Role
Automotive Phys including Automotive Ethernet/SerDes research and development with Design and simulation
Provide the DSP spec and RTL validation support
Responsibility: Building up the channel model and simulation platform in MATLAB or C
Transceiver block design and performance evaluations based on the simulations
DSP chip bring-up, lab data collection, and chip debugging with the DSP support for the RMAs
Your Profile Qualifications and skills to help you succeed:
EE Ph.D degree with 0-1 years or Master's degree with 1-3 years of work experience
Knowledge of Digital Signal Processing, Digital Communication Theory, and Transmission Line Theory
Basic knowledge of Digital Design. Basic knowledge of Analog Design, Electro‑Magnetic Compliance, or Forward Error Correction theory is a plus
Familiar with MATLAB and C++ languages
RTL coding is a plus
Infineon Technologies Americas Corp., is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), gender identity, national origin, ancestry, citizenship, age, physical or mental disability, legally protected medical condition, family care status, military or veteran status, marital status, domestic partner status, sexual orientation, or any other basis protected by local, state, or federal laws. Employment at Infineon is contingent upon proof of your legal right to work in the United States under applicable law, verification of satisfactory references and successful completion of a background check and drug test, and signing all your on-boarding documents. In some instances, if applicable, U.S. export control laws require that Infineon obtain a U.S. government export license prior to releasing technologies to certain persons. This offer is contingent upon Infineon's ability to satisfy these export control laws as related to your employment and anticipated job activities. The decision whether or not to submit and/or pursue an export license to satisfy this contingency, if applicable, shall be at Infineon's sole discretion.
Infineon Technologies takes data privacy and identity theft very seriously. As such, we do not request personally identifiable information (PII) from applicants over the internet or electronically. Please kindly refrain from disclosing your PII electronically during the application process or to unauthorized websites that may purport to be Infineon or any of our affiliates.
In the United States, it is required to disclose a salary range to applicants. The salary range that the company expects to pay for a qualified candidate in the United States is: San Jose, CA - Minimum of $125,680.00 per year / Maximum of $172,810.00 per year. In addition, all employees will be eligible to participate in an incentive plan.
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Your Role
Automotive Phys including Automotive Ethernet/SerDes research and development with Design and simulation
Provide the DSP spec and RTL validation support
Responsibility: Building up the channel model and simulation platform in MATLAB or C
Transceiver block design and performance evaluations based on the simulations
DSP chip bring-up, lab data collection, and chip debugging with the DSP support for the RMAs
Your Profile Qualifications and skills to help you succeed:
EE Ph.D degree with 0-1 years or Master's degree with 1-3 years of work experience
Knowledge of Digital Signal Processing, Digital Communication Theory, and Transmission Line Theory
Basic knowledge of Digital Design. Basic knowledge of Analog Design, Electro‑Magnetic Compliance, or Forward Error Correction theory is a plus
Familiar with MATLAB and C++ languages
RTL coding is a plus
Infineon Technologies Americas Corp., is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), gender identity, national origin, ancestry, citizenship, age, physical or mental disability, legally protected medical condition, family care status, military or veteran status, marital status, domestic partner status, sexual orientation, or any other basis protected by local, state, or federal laws. Employment at Infineon is contingent upon proof of your legal right to work in the United States under applicable law, verification of satisfactory references and successful completion of a background check and drug test, and signing all your on-boarding documents. In some instances, if applicable, U.S. export control laws require that Infineon obtain a U.S. government export license prior to releasing technologies to certain persons. This offer is contingent upon Infineon's ability to satisfy these export control laws as related to your employment and anticipated job activities. The decision whether or not to submit and/or pursue an export license to satisfy this contingency, if applicable, shall be at Infineon's sole discretion.
Infineon Technologies takes data privacy and identity theft very seriously. As such, we do not request personally identifiable information (PII) from applicants over the internet or electronically. Please kindly refrain from disclosing your PII electronically during the application process or to unauthorized websites that may purport to be Infineon or any of our affiliates.
In the United States, it is required to disclose a salary range to applicants. The salary range that the company expects to pay for a qualified candidate in the United States is: San Jose, CA - Minimum of $125,680.00 per year / Maximum of $172,810.00 per year. In addition, all employees will be eligible to participate in an incentive plan.
#J-18808-Ljbffr