ObjectWin Technology
100% Onsite role in San Jose, CA.
Duration: 6 months (strong possibility of extension based on performance).
Lab/PVT Validation Engineer Top Must Have Skills
3+ years of hands‑on experience in an electronics lab running PVT or HAST/HTOL‑type testing on FPGAs, SoCs, or high‑speed digital boards.
Experience with lab instruments: thermal chambers (Thermotron, Espec), thermal stream (Temptronic, AccuStream), oscilloscopes (Keysight, Tektronix), spectrum analyzers, VNA, TDR, programmable power supplies (Chroma, Keysight N6700/N7900), and source‑measure units (SMU).
Familiarity with FPGA tools (Vivado Lab Edition, Vivado Hardware Manager, ILA/VIO) and basic bitstream loading via JTAG or flash.
Strong troubleshooting and debugging skills; able to work independently to isolate whether an issue is silicon, board, package, power delivery, or thermal related.
Primary Responsibilities
Execute comprehensive PVT (Process, Voltage, Temperature) characterization on the latest AMD FPGA families (Versal™, UltraScale+™, 7nm/6nm/5nm nodes) mounted on multiple validation, characterization, and customer reference boards.
Operate and maintain environmental chambers, thermal stream systems, temperature‑forced air systems, DC parametric analyzers, high‑speed oscilloscopes, TDRs, VNAs, and programmable power supplies.
Develop, debug, and maintain automation scripts (Python preferred, Tcl/Python/Perl acceptable) to control instruments, power supplies, thermal systems, and the FPGA design running on the board (via JTAG, UART, Ethernet, or PCIe).
Perform shmoo testing across voltage corners (Vccint, Vccaux, VCCO, etc.), temperature range (–40°C to +125°C typical), and process corners (FF/SS/TT, slow/fast die IDs).
Collect, post‑process, and plot large data sets (timing margins, power consumption, eye diagrams, jitter, IDD vs. temperature/voltage, etc.) and upload results to central databases.
Work daily with FPGA board design engineers, Signal Integrity (SI), Power Integrity (PI), and silicon characterization teams to root‑cause failures (e.g., marginal timing, excessive voltage droop, thermal runaway, PLL lock issues).
Assist in debugging high‑speed DDR4/LPDDR5 interfaces under worst‑case PVT conditions.
Document test procedures, failures, and resolution steps in Confluence/JIRA and maintain version‑controlled automation code in Git.
Required Skills & Experience
Associate's or Bachelor's degree in Electrical/Electronic Technology, or equivalent experience.
3+ years of hands‑on experience in an electronics lab running PVT or HAST/HTOL‑type testing on FPGAs, SoCs, or high‑speed digital boards.
Proficient in Python/TCL/Perl scripting for test automation (instrument control via pyvisa, scpi, serial/I2C/JTAG communication, data parsing, plotting with matplotlib/pandas).
Solid understanding of DC and AC parametric testing, shmoo plots, margin testing, and guard‑banging concepts.
Experience with lab instruments: thermal chambers (Thermotron, Espec), thermal stream (Temptronic, AccuStream), oscilloscopes (Keysight, Tektronix), spectrum analyzers, VNA, TDR, programmable power supplies (Chroma, Keysight N6700/N7900), and source‑measure units (SMU).
Comfortable reading schematics, identifying test points, and probing high‑density boards (10+ layer, 0.5 mm pitch BGA).
Familiarity with FPGA tools (Vivado Lab Edition, Vivado Hardware Manager, ILA/VIO) and basic bitstream loading via JTAG or flash.
Strong troubleshooting and debugging skills; able to work independently to isolate whether an issue is silicon, board, package, power delivery, or thermal related.
Excellent written and verbal communication; must be able to present findings clearly to SI/PI engineers and management.
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Duration: 6 months (strong possibility of extension based on performance).
Lab/PVT Validation Engineer Top Must Have Skills
3+ years of hands‑on experience in an electronics lab running PVT or HAST/HTOL‑type testing on FPGAs, SoCs, or high‑speed digital boards.
Experience with lab instruments: thermal chambers (Thermotron, Espec), thermal stream (Temptronic, AccuStream), oscilloscopes (Keysight, Tektronix), spectrum analyzers, VNA, TDR, programmable power supplies (Chroma, Keysight N6700/N7900), and source‑measure units (SMU).
Familiarity with FPGA tools (Vivado Lab Edition, Vivado Hardware Manager, ILA/VIO) and basic bitstream loading via JTAG or flash.
Strong troubleshooting and debugging skills; able to work independently to isolate whether an issue is silicon, board, package, power delivery, or thermal related.
Primary Responsibilities
Execute comprehensive PVT (Process, Voltage, Temperature) characterization on the latest AMD FPGA families (Versal™, UltraScale+™, 7nm/6nm/5nm nodes) mounted on multiple validation, characterization, and customer reference boards.
Operate and maintain environmental chambers, thermal stream systems, temperature‑forced air systems, DC parametric analyzers, high‑speed oscilloscopes, TDRs, VNAs, and programmable power supplies.
Develop, debug, and maintain automation scripts (Python preferred, Tcl/Python/Perl acceptable) to control instruments, power supplies, thermal systems, and the FPGA design running on the board (via JTAG, UART, Ethernet, or PCIe).
Perform shmoo testing across voltage corners (Vccint, Vccaux, VCCO, etc.), temperature range (–40°C to +125°C typical), and process corners (FF/SS/TT, slow/fast die IDs).
Collect, post‑process, and plot large data sets (timing margins, power consumption, eye diagrams, jitter, IDD vs. temperature/voltage, etc.) and upload results to central databases.
Work daily with FPGA board design engineers, Signal Integrity (SI), Power Integrity (PI), and silicon characterization teams to root‑cause failures (e.g., marginal timing, excessive voltage droop, thermal runaway, PLL lock issues).
Assist in debugging high‑speed DDR4/LPDDR5 interfaces under worst‑case PVT conditions.
Document test procedures, failures, and resolution steps in Confluence/JIRA and maintain version‑controlled automation code in Git.
Required Skills & Experience
Associate's or Bachelor's degree in Electrical/Electronic Technology, or equivalent experience.
3+ years of hands‑on experience in an electronics lab running PVT or HAST/HTOL‑type testing on FPGAs, SoCs, or high‑speed digital boards.
Proficient in Python/TCL/Perl scripting for test automation (instrument control via pyvisa, scpi, serial/I2C/JTAG communication, data parsing, plotting with matplotlib/pandas).
Solid understanding of DC and AC parametric testing, shmoo plots, margin testing, and guard‑banging concepts.
Experience with lab instruments: thermal chambers (Thermotron, Espec), thermal stream (Temptronic, AccuStream), oscilloscopes (Keysight, Tektronix), spectrum analyzers, VNA, TDR, programmable power supplies (Chroma, Keysight N6700/N7900), and source‑measure units (SMU).
Comfortable reading schematics, identifying test points, and probing high‑density boards (10+ layer, 0.5 mm pitch BGA).
Familiarity with FPGA tools (Vivado Lab Edition, Vivado Hardware Manager, ILA/VIO) and basic bitstream loading via JTAG or flash.
Strong troubleshooting and debugging skills; able to work independently to isolate whether an issue is silicon, board, package, power delivery, or thermal related.
Excellent written and verbal communication; must be able to present findings clearly to SI/PI engineers and management.
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