Senior ASIC Verification Engineer – DDR5/RTL, SystemVerilog

A technology company located in Santa Clara, CA, is seeking a Design Verification Engineer with at least 8 years of experience. This hybrid role involves developing verification tests and collaborating with engineers across different sites to ensure quality in modern processor architecture. Strong skills in System Verilog, UVM, and debugging are essential. Candidates should have a Bachelor's or Master's degree in Computer Engineering or Electrical Engineering. The position offers flexibility to work remotely, preferably within the PST time zone. #J-18808-Ljbffr