Senior ASIC/RTL Verification Engineer – DDR5/SystemVerilog

A leading technology company in Santa Clara is seeking an experienced Design Verification Engineer to contribute to innovative processor architecture and digital design projects. The ideal candidate will have at least 8 years of design verification experience, strong skills in System Verilog and UVM, and the ability to collaborate across teams. You will be responsible for developing verification tests, debugging failures, and providing technical support. Join a dynamic environment focused on delivering industry-leading technologies. #J-18808-Ljbffr