Senior FPGA Verification Engineer – SystemVerilog/UVM

A leading technology firm in El Segundo, California is seeking a Mid-Senior level Design Engineer for a contract role specializing in ASIC and FPGA verification. The ideal candidate will have over 10 years of experience in design engineering, particularly in functional verification, utilizing SystemVerilog and UVM. Preferred qualifications include a BSEE or BSCS degree, and candidates must be U.S. citizens eligible for DoD security clearance. This position offers competitive pay based on skills and experience. #J-18808-Ljbffr