Lead Validation Engineer - DDR Memory Interfaces & SI/PI

A leading chip and silicon IP provider is seeking an experienced Validation Manager to join its Memory Interface Chip business unit in San Jose, CA. This role encompasses hands-on technical work combined with overseeing a small team of validation engineers. The ideal candidate will have extensive experience in validation, particularly with DDR4/DDR5 memory interfaces, and strong skills in Python scripting. A competitive salary range of $170,000 to $210,000 per year is offered depending on experience. #J-18808-Ljbffr