Senior ASIC Verification Architect - SystemVerilog/UVM

A leading semiconductor firm in California is seeking an experienced IC Verification Engineer to architect scalable Testbench environments. The role demands 10+ years in verification with proficiency in System Verilog and methodologies like UVM. Candidates will drive test plans and debug regression failures while mentoring junior team members. The position offers a competitive salary and comprehensive benefits, including medical coverage and a retirement plan. #J-18808-Ljbffr