Lead ASIC Verification Engineer (SystemVerilog/UVM)

A leading semiconductor company in San Jose, California is looking for an experienced ASIC Verification Engineer. This role demands a minimum of 10 years in developing complex Verification Environments and a proficient understanding of System Verilog and Verification Methodologies. Candidates should have experience with PCI Express and leadership abilities to mentor junior engineers. The company offers a competitive salary range of $141,300 to $226,000 along with comprehensive benefits, including medical, dental, and 401(K) plans. #J-18808-Ljbffr