Senior Interconnect Micro-Architect & RTL Lead

A leading semiconductor company seeks an engineering leader to drive Power, Performance, and Area (PPA) in their data fabrics IPs for next-gen AI devices. You will lead scalable, complex digital IP designs and collaborate with various teams to ensure optimal RTL execution. The ideal candidate will have expertise in SOC methodologies and strong skills in digital design, communication, and collaboration across multiple teams. This role is located in Santa Clara, California and offers opportunities to innovate in the field of artificial intelligence. #J-18808-Ljbffr