Lead Data Fabric Microarchitecture & RTL Design Engineer

A leading technology company in Santa Clara is seeking an engineering leader to drive the best Power, Performance, Area (PPA) for Data Fabrics IPs in AMD's AI devices. The ideal candidate will have a proven track record in creating scalable digital microarchitectures and will work closely with various teams to ensure the successful delivery of complex SoCs. Candidates must possess excellent leadership, communication, and collaboration skills. A background in computer engineering or electrical engineering is preferred. #J-18808-Ljbffr