Apex Systems
Hardware Engineering and R&D - Hardware Design Engineer 3
Apex Systems, Indiana, Pennsylvania, us, 15705
Hardware Engineering and R&D - Hardware Design Engineer 3
1 day ago Be among the first 25 applicants
This range is provided by Apex Systems. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
Base pay range $50.00/hr - $60.00/hr
Job Information Job#:
3015287
Title:
Hardware Design Engineer 3
Start Date:
01/26/2026
Duration:
~18 months
Chance for Extension:
Highly likely
Location:
Fully Remote (Domestic US, anywhere in continental US)
Openings:
1
Top 3 Hard Skills Required
Analog circuit layout in advanced CMOS (FinFET/gate-all-around, 2–3nm) – 4+ years
Proficiency with layout tools (Cadence Virtuoso, Calibre) – 4+ years
Understanding of analog layout techniques (matching, shielding, reliability, parasitic optimization) – 4+ years
Candidate Requirements
Overall Experience: 5+ years in the field
Degree/Certifications: Not required
Ideal Candidate:
Recent experience with CMOS layout and verification on advanced FinFET and GAA
Experience with advanced PSMC nodes is a big plus
Experienced in advanced CMOS (2–3nm) and analog layout
Typical Day
Team Purpose: Analog mixed‑signal IPs for in‑house SoC designs (data center processors, advanced CMOS tech)
Key Projects: Layout for analog mixed‑signal circuits in 2–3nm nodes
Task Breakdown:
80% hands‑down design/layout work
20% meetings
Focus: Analog layout (not custom digital)
Compelling Story
Work on cutting‑edge analog layout in FinFET and gate‑all‑around technologies (2–3nm)—rare and highly valued in the industry.
Key Responsibilities
Execute full‑custom layout for analog/mixed‑signal blocks (ADCs, DACs, PLLs, LDOs, comparators, temperature sensors)
Collaborate with circuit designers for performance, area, and power optimization
Perform floorplanning, block‑level routing, macro‑level assembly
Conduct physical verification (Cadence Virtuoso, Synopsys Custom Compiler, Calibre)
Address DRC/LVS, EMIR, DFM issues; ensure reliability standards
Support tape‑out activities and post‑layout simulation reviews
Document layout strategies and contribute to design reviews
EEO Employer Apex Systems is an equal opportunity employer. We do not discriminate or allow discrimination on the basis of race, color, religion, creed, sex (including pregnancy, childbirth, breastfeeding, or related medical conditions), age, sexual orientation, gender identity, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, disability, status as a crime victim, protected veteran status, political affiliation, union membership, or any other characteristic protected by law. Apex will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable law. If you have visited our website in search of information on employment opportunities or to apply for a position, and you require an accommodation in using our website for a search or application, please contact our Employee Services Department at
careers@apexsystems.com
or 844‑463‑6178.
#J-18808-Ljbffr
This range is provided by Apex Systems. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
Base pay range $50.00/hr - $60.00/hr
Job Information Job#:
3015287
Title:
Hardware Design Engineer 3
Start Date:
01/26/2026
Duration:
~18 months
Chance for Extension:
Highly likely
Location:
Fully Remote (Domestic US, anywhere in continental US)
Openings:
1
Top 3 Hard Skills Required
Analog circuit layout in advanced CMOS (FinFET/gate-all-around, 2–3nm) – 4+ years
Proficiency with layout tools (Cadence Virtuoso, Calibre) – 4+ years
Understanding of analog layout techniques (matching, shielding, reliability, parasitic optimization) – 4+ years
Candidate Requirements
Overall Experience: 5+ years in the field
Degree/Certifications: Not required
Ideal Candidate:
Recent experience with CMOS layout and verification on advanced FinFET and GAA
Experience with advanced PSMC nodes is a big plus
Experienced in advanced CMOS (2–3nm) and analog layout
Typical Day
Team Purpose: Analog mixed‑signal IPs for in‑house SoC designs (data center processors, advanced CMOS tech)
Key Projects: Layout for analog mixed‑signal circuits in 2–3nm nodes
Task Breakdown:
80% hands‑down design/layout work
20% meetings
Focus: Analog layout (not custom digital)
Compelling Story
Work on cutting‑edge analog layout in FinFET and gate‑all‑around technologies (2–3nm)—rare and highly valued in the industry.
Key Responsibilities
Execute full‑custom layout for analog/mixed‑signal blocks (ADCs, DACs, PLLs, LDOs, comparators, temperature sensors)
Collaborate with circuit designers for performance, area, and power optimization
Perform floorplanning, block‑level routing, macro‑level assembly
Conduct physical verification (Cadence Virtuoso, Synopsys Custom Compiler, Calibre)
Address DRC/LVS, EMIR, DFM issues; ensure reliability standards
Support tape‑out activities and post‑layout simulation reviews
Document layout strategies and contribute to design reviews
EEO Employer Apex Systems is an equal opportunity employer. We do not discriminate or allow discrimination on the basis of race, color, religion, creed, sex (including pregnancy, childbirth, breastfeeding, or related medical conditions), age, sexual orientation, gender identity, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, disability, status as a crime victim, protected veteran status, political affiliation, union membership, or any other characteristic protected by law. Apex will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable law. If you have visited our website in search of information on employment opportunities or to apply for a position, and you require an accommodation in using our website for a search or application, please contact our Employee Services Department at
careers@apexsystems.com
or 844‑463‑6178.
#J-18808-Ljbffr