Apex Systems
Hardware Engineering and R&D - Hardware Design Engineer 3
Apex Systems, Redmond, Washington, United States, 98052
## Job Description# Hardware Engineering and R&D - Hardware Design Engineer 31. Analog circuit layout in advanced CMOS (FinFET/gate-all-around, 2–3nm) – **4+ years**2. Proficiency with layout tools (Cadence Virtuoso, Calibre) – **4+ years**3. Understanding of analog layout techniques (matching, shielding, reliability, parasitic optimization) – **4+ years*** **Overall Experience:** 5+ years in the field* **Degree/Certifications:** Not required* **Ideal Candidate:**
+ Recent experience with CMOS layout and verification on advanced FinFET and GAA
+ Experience with advanced PSMC nodes is a big plus
+ Experienced in advanced CMOS (2–3nm) and analog layout* **Team Purpose:** Analog mixed-signal IPs for in-house SoC designs (data center processors, advanced CMOS tech)* **Key Projects:** Layout for analog mixed-signal circuits in 2–3nm nodes* **Task Breakdown:**
+ 80% hands-down design/layout work
+ 20% meetings* **Focus:** Analog layout (not custom digital) #J-18808-Ljbffr
+ Recent experience with CMOS layout and verification on advanced FinFET and GAA
+ Experience with advanced PSMC nodes is a big plus
+ Experienced in advanced CMOS (2–3nm) and analog layout* **Team Purpose:** Analog mixed-signal IPs for in-house SoC designs (data center processors, advanced CMOS tech)* **Key Projects:** Layout for analog mixed-signal circuits in 2–3nm nodes* **Task Breakdown:**
+ 80% hands-down design/layout work
+ 20% meetings* **Focus:** Analog layout (not custom digital) #J-18808-Ljbffr