Credo
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Credo is engineering the future of high-speed connectivity for the AI-driven world.
With a deeply rooted legacy of innovation and a passion for solving the most complex networking challenges, we deliver industry-leading solutions that power the next generation of cloud, AI, and hyperscale data centers. Credo is pioneering a systems-level approach to connectivity, integrating hardware, software, and architecture to deliver holistic solutions. This strategy not only differentiates us in the market but also creates significant value for our customers by accelerating deployment, improving performance, and reducing complexity across their infrastructure. At Credo, you’ll be part of a team of world-class technologists and engineers that thrive on pushing the limits of what’s possible for some of the world’s most important companies. Our portfolio includes cutting edge solutions including our software,
optical DSPs, PCIe/CXL products, SerDes IP, and advanced Active Electrical Cables
(AECs) all designed for maximum performance, energy efficiency, and scalability. We foster a culture of
technical excellence, collaboration, and continuous learning , where your ideas can shape the future of connectivity. From silicon architects to systems engineers, every role at Credo contributes to solving real-world problems at scale. Join us and help us architect the next generation of disruptive networking technologies — because at Credo, We Connect . About the role
As a Design Verification Engineer, you will ensure the quality and performance of complex digital designs through rigorous verification. You’ll develop and execute verification plans, build scalable reusable testbenches, write SV‑UVM sequences, debug issues, and collaborate closely with RTL designers and firmware/application engineering teams. Key Responsibilities
Understand design intent and develop comprehensive verification & test plans Develop reusable, scalable SV‑UVM testbenches and write test sequences Verify PCIe subsystems and other interfaces (I2C/I3C/SMBus/CPU/UART/SPI) at block and subsystem levels (e.g., PHY, controller) Write assertions, checkers, and coverage, analyze functional & code coverage gaps, and drive closure Build firmware‑based simulations in C; mirror/approximate real FW behavior to validate HW/SW interactions Reproduce silicon failures in simulation and perform deep debug to root cause Automate flows with Python/Perl/Shell scripting Collaborate with AEs/FW on debug, feature implementation, and spec contributions driven by DV findings Basic Qualifications
BS/MS in Electrical Engineering, Computer Engineering, or related field 7+ years of experience in RTL and functional verification using SV/UVM Experience with gate‑level simulation and firmware‑based simulation Proficiency in RTL design and computer architecture concepts Strong debugging, problem‑solving, and analytical skills Effective collaborator who thrives in cross‑functional teams Preferred Qualifications
Background in high‑speed connectivity solutions (PCIe/CXL, SerDes, optical DSP) Experience working across HW/SW boundaries and with application engineering/firmware teams The base salary range for this position is $130,000 to $160,000 per year. The base salary ultimately offered is determined through a review of education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits. Credo is an Equal Opportunity Employer. We are committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email people@credosemi.com.
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With a deeply rooted legacy of innovation and a passion for solving the most complex networking challenges, we deliver industry-leading solutions that power the next generation of cloud, AI, and hyperscale data centers. Credo is pioneering a systems-level approach to connectivity, integrating hardware, software, and architecture to deliver holistic solutions. This strategy not only differentiates us in the market but also creates significant value for our customers by accelerating deployment, improving performance, and reducing complexity across their infrastructure. At Credo, you’ll be part of a team of world-class technologists and engineers that thrive on pushing the limits of what’s possible for some of the world’s most important companies. Our portfolio includes cutting edge solutions including our software,
optical DSPs, PCIe/CXL products, SerDes IP, and advanced Active Electrical Cables
(AECs) all designed for maximum performance, energy efficiency, and scalability. We foster a culture of
technical excellence, collaboration, and continuous learning , where your ideas can shape the future of connectivity. From silicon architects to systems engineers, every role at Credo contributes to solving real-world problems at scale. Join us and help us architect the next generation of disruptive networking technologies — because at Credo, We Connect . About the role
As a Design Verification Engineer, you will ensure the quality and performance of complex digital designs through rigorous verification. You’ll develop and execute verification plans, build scalable reusable testbenches, write SV‑UVM sequences, debug issues, and collaborate closely with RTL designers and firmware/application engineering teams. Key Responsibilities
Understand design intent and develop comprehensive verification & test plans Develop reusable, scalable SV‑UVM testbenches and write test sequences Verify PCIe subsystems and other interfaces (I2C/I3C/SMBus/CPU/UART/SPI) at block and subsystem levels (e.g., PHY, controller) Write assertions, checkers, and coverage, analyze functional & code coverage gaps, and drive closure Build firmware‑based simulations in C; mirror/approximate real FW behavior to validate HW/SW interactions Reproduce silicon failures in simulation and perform deep debug to root cause Automate flows with Python/Perl/Shell scripting Collaborate with AEs/FW on debug, feature implementation, and spec contributions driven by DV findings Basic Qualifications
BS/MS in Electrical Engineering, Computer Engineering, or related field 7+ years of experience in RTL and functional verification using SV/UVM Experience with gate‑level simulation and firmware‑based simulation Proficiency in RTL design and computer architecture concepts Strong debugging, problem‑solving, and analytical skills Effective collaborator who thrives in cross‑functional teams Preferred Qualifications
Background in high‑speed connectivity solutions (PCIe/CXL, SerDes, optical DSP) Experience working across HW/SW boundaries and with application engineering/firmware teams The base salary range for this position is $130,000 to $160,000 per year. The base salary ultimately offered is determined through a review of education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits. Credo is an Equal Opportunity Employer. We are committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email people@credosemi.com.
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