Renesas Electronics
Senior Staff MOCVD Development Engineer
The Senior Staff MOCVD Development Engineer will lead process and hardware development for GaN-based epitaxial growth on silicon and sapphire substrates, enabling next-generation power devices. This role emphasizes deep technical understanding of MOCVD reactor behavior, GaN heterostructure engineering, and epitaxial integration for p-GaN and e-mode (enhancement-mode) device architectures. The ideal candidate combines strong experimental rigor, demonstrated materials expertise, and cross‑functional leadership to translate research concepts into production‑capable processes.
Responsibilities
Develop, optimize, and transfer MOCVD epitaxial processes for GaN-on‑Si and GaN-on‑Sapphire wafers, focusing on high‑performance device layers targeting e‑mode (p‑GaN gate) and HEMT applications.
Design and execute development roadmaps for buffer structure engineering, strain management, and defect reduction to achieve target breakdown voltages, leakage, and mobility metrics.
Lead process integration studies addressing p‑type activation, Mg incorporation, compensation control, and interface optimization for gate reliability.
Drive reactor‑scale modeling and hardware tuning to improve growth uniformity, thickness control, and wafer bow mitigation on large‑diameter substrates.
Analyze defect physics mechanisms (threading dislocations, V‑defects, point defects) affecting device reliability and performance, driving iterative improvements in process conditions.
Design and execute structured experiments (DOE‑based) to deconvolve multi‑parameter interactions in reactor conditions, precursor chemistry, and thermal profiles.
Characterize epitaxial films using XRD, AFM, TEM, PL, CV, and Hall measurements, correlating data to growth parameters and device performance.
Collaborate closely with device engineers and reliability teams to co‑optimize epitaxial structures for threshold voltage, dynamic RON, off‑state leakage, and long‑term stability.
Translate device performance specifications and reliability requirements into detailed epitaxial process and material specifications; document Process of Record (PoR) and engineering specifications for qualification and manufacturing handoff.
Support failure analysis, root cause investigations, and corrective action implementation for process‑related device excursions or reliability issues.
Lead process transfer activities from R&D to pilot or production‑scale reactors, ensuring knowledge capture and robust parameter windows.
Qualifications
Education: Ph.D. in Materials Science, Electrical Engineering, Physics, or closely related discipline. M.S. with 10+ years of directly relevant hands‑on experience.
Minimum 8+ years of direct hands‑on MOCVD process development and optimization for III‑V or III‑nitride semiconductor materials (GaN, AlGaN, InGaN, etc.).
Demonstrated technical expertise in GaN‑on‑Si and/or GaN‑on‑Sapphire heterostructures, including buffer layer design, strain engineering, and defect reduction strategies.
Strong experience developing p‑type GaN epitaxy and e‑mode device architectures, with deep understanding of Mg activation, dopant diffusion control, and gate stack engineering for threshold voltage stability.
Proficiency with advanced epitaxial layer characterization techniques (XRD, SIMS, CL, TEM, PL, Hall effect measurements) and ability to interpret results to guide process optimization.
Track record of designing complex DOEs, executing structured experiments, conducting statistical analysis (SPC, multivariate data interpretation), and drawing evidence‑based conclusions. Demonstrated success in transferring epitaxial processes from R&D to pilot or high‑volume manufacturing environments, with understanding of manufacturability constraints and yield optimization.
Excellent written and verbal communication skills.
Experience with multiple MOCVD platforms (e.g., Aixtron G5, G4, or Veeco Propel systems) – preferred.
Familiarity with GaN power device design requirements and performance metrics – preferred.
Prior leadership or mentoring experience in an R&D or manufacturing engineering environment – preferred.
Additional Information Expected annual pay range: $180K‑$220K. Eligible for bonus opportunities. Final offer depends on geographic location, experience, and skill set.
Full range of elective benefits: medical, dental, vision, health savings account with applicable medical plan, dependent care flexible spending accounts, pre‑tax commuter benefits, life insurance, AD&D, pet insurance. Employees also receive company‑paid life insurance and AD&D, LTD, short‑term medical benefits, paid sick time, paid holidays, and accrued paid vacation. New employees attend a detailed benefit orientation.
Renesas offers professionals a flexible, inclusive environment with remote work two days per week and in‑office collaboration on Tuesdays through Thursdays.
At Renesas, You Can
Launch and advance your career in technical and business roles across four Product Groups and various corporate functions, exploring hardware and software capabilities.
Make a real impact by developing innovative products and solutions for global customers, helping make people’s lives easier, safe, and secure.
Maximize your performance and wellbeing in our flexible and inclusive work environment and global support system, including remote work options and Employee Resource Groups.
Equal Opportunity and Diversity Statement Renesas Electronics is an equal‑opportunity and affirmative action employer, committed to celebrating diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by federal, state or local law. For more information, please read our Diversity & Inclusion Statement.
Export Control Notification Renesas Electronics deals with dual‑use technology subject to U.S. export control regulations. Renesas may need to obtain a U.S. government export license prior to releasing technology to certain persons. The decision to file or pursue an export license application is at Renesas’ discretion.
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Responsibilities
Develop, optimize, and transfer MOCVD epitaxial processes for GaN-on‑Si and GaN-on‑Sapphire wafers, focusing on high‑performance device layers targeting e‑mode (p‑GaN gate) and HEMT applications.
Design and execute development roadmaps for buffer structure engineering, strain management, and defect reduction to achieve target breakdown voltages, leakage, and mobility metrics.
Lead process integration studies addressing p‑type activation, Mg incorporation, compensation control, and interface optimization for gate reliability.
Drive reactor‑scale modeling and hardware tuning to improve growth uniformity, thickness control, and wafer bow mitigation on large‑diameter substrates.
Analyze defect physics mechanisms (threading dislocations, V‑defects, point defects) affecting device reliability and performance, driving iterative improvements in process conditions.
Design and execute structured experiments (DOE‑based) to deconvolve multi‑parameter interactions in reactor conditions, precursor chemistry, and thermal profiles.
Characterize epitaxial films using XRD, AFM, TEM, PL, CV, and Hall measurements, correlating data to growth parameters and device performance.
Collaborate closely with device engineers and reliability teams to co‑optimize epitaxial structures for threshold voltage, dynamic RON, off‑state leakage, and long‑term stability.
Translate device performance specifications and reliability requirements into detailed epitaxial process and material specifications; document Process of Record (PoR) and engineering specifications for qualification and manufacturing handoff.
Support failure analysis, root cause investigations, and corrective action implementation for process‑related device excursions or reliability issues.
Lead process transfer activities from R&D to pilot or production‑scale reactors, ensuring knowledge capture and robust parameter windows.
Qualifications
Education: Ph.D. in Materials Science, Electrical Engineering, Physics, or closely related discipline. M.S. with 10+ years of directly relevant hands‑on experience.
Minimum 8+ years of direct hands‑on MOCVD process development and optimization for III‑V or III‑nitride semiconductor materials (GaN, AlGaN, InGaN, etc.).
Demonstrated technical expertise in GaN‑on‑Si and/or GaN‑on‑Sapphire heterostructures, including buffer layer design, strain engineering, and defect reduction strategies.
Strong experience developing p‑type GaN epitaxy and e‑mode device architectures, with deep understanding of Mg activation, dopant diffusion control, and gate stack engineering for threshold voltage stability.
Proficiency with advanced epitaxial layer characterization techniques (XRD, SIMS, CL, TEM, PL, Hall effect measurements) and ability to interpret results to guide process optimization.
Track record of designing complex DOEs, executing structured experiments, conducting statistical analysis (SPC, multivariate data interpretation), and drawing evidence‑based conclusions. Demonstrated success in transferring epitaxial processes from R&D to pilot or high‑volume manufacturing environments, with understanding of manufacturability constraints and yield optimization.
Excellent written and verbal communication skills.
Experience with multiple MOCVD platforms (e.g., Aixtron G5, G4, or Veeco Propel systems) – preferred.
Familiarity with GaN power device design requirements and performance metrics – preferred.
Prior leadership or mentoring experience in an R&D or manufacturing engineering environment – preferred.
Additional Information Expected annual pay range: $180K‑$220K. Eligible for bonus opportunities. Final offer depends on geographic location, experience, and skill set.
Full range of elective benefits: medical, dental, vision, health savings account with applicable medical plan, dependent care flexible spending accounts, pre‑tax commuter benefits, life insurance, AD&D, pet insurance. Employees also receive company‑paid life insurance and AD&D, LTD, short‑term medical benefits, paid sick time, paid holidays, and accrued paid vacation. New employees attend a detailed benefit orientation.
Renesas offers professionals a flexible, inclusive environment with remote work two days per week and in‑office collaboration on Tuesdays through Thursdays.
At Renesas, You Can
Launch and advance your career in technical and business roles across four Product Groups and various corporate functions, exploring hardware and software capabilities.
Make a real impact by developing innovative products and solutions for global customers, helping make people’s lives easier, safe, and secure.
Maximize your performance and wellbeing in our flexible and inclusive work environment and global support system, including remote work options and Employee Resource Groups.
Equal Opportunity and Diversity Statement Renesas Electronics is an equal‑opportunity and affirmative action employer, committed to celebrating diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by federal, state or local law. For more information, please read our Diversity & Inclusion Statement.
Export Control Notification Renesas Electronics deals with dual‑use technology subject to U.S. export control regulations. Renesas may need to obtain a U.S. government export license prior to releasing technology to certain persons. The decision to file or pursue an export license application is at Renesas’ discretion.
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