Performance Modeling & Verification Engineer - SystemC/TLM

A technology solutions company based in Santa Clara seeks a SystemC Modeling Engineer with at least 5 years of relevant experience. The role involves developing and maintaining SystemC/TLM2 models for various memory controllers and peripherals. Candidates should be proficient in C/C++ programming and possess a strong grasp of Transaction-Level Modeling concepts. The company offers a hybrid working model, allowing remote work flexibility. #J-18808-Ljbffr