Senior ASIC/RTL Design & Verification Engineer (DDR5)

A global workforce management provider is seeking an experienced Design Verification Engineer to enhance capabilities in delivering high-quality semiconductor technologies. Located in Santa Clara, CA, the role demands expertise in Design Verification, including DDR5 Controller and system languages like System Verilog. Applicants should possess strong analytical skills and solid communication abilities for effective collaboration across teams. This position offers a competitive pay rate and the chance to contribute to leading-edge projects in the semiconductor field. #J-18808-Ljbffr