Acceler8 Talent
Senior Firmware Engineer (San Francisco)
Acceler8 Talent, San Francisco, California, United States, 94199
Senior Firmware Engineer - San Francisco, CA
A company building AI systems that can interact with the physical world at scale - designing experiments, controlling hardware, and accelerating scientific discovery from days to reality are looking for a Senior Firmware Engineer to join their team.
What Will I Be Doing
Design auto-generation flows transforming specs into deterministic firmware/RTL, including register maps, FSMs, and memory-mapped interfaces Own digital design correctness: clock/reset domains, CDC, timing constraints, and synthesis-aware RTL for FPGA/ASIC workflows Build integration layers for standard protocols (UART, SPI, I2C, CAN, Ethernet) and internal buses (AXI, APB, Wishbone) Develop verification infrastructure: self-checking testbenches, SVA, linting, coverage-driven regression, and formal methods Create tool-driven feedback loops running synthesis/simulation/formal verification with automatic fix proposals Ship CI/CD systems with golden tests, build determinism, and strict change controls Implement safety guardrails: invariants, privilege boundaries, audit logging, and policies preventing unsafe outputs Collaborate with platform, ML/agent, and domain teams to integrate into live hardware workflows
What We're Looking For
Strong digital design: FSM design, register maps, timing/constraints, CDC, hardware debug Hardware protocol integration and memory-mapped control patterns Verification skills: testbenches, SVA/assertions, UVM concepts, simulation tools (Verilator, commercial) FPGA/ASIC flow knowledge and ability to deliver synthesizable, timing-clean RTL Experience building reproducible automation pipelines: deterministic codegen, error parsing, CI/CD AI-powered code generation pipeline experience: spec
structured IR, templating, tool-calling loops, safety mechanisms Strong software engineering: clean architecture, testing, versioning, reliability mindset
What's In It For Me:
Salary of $200,000 - $300,000 dependent on experience Greenfield work. Build something that doesn't exist, at the frontier of physical AI and automated hardware design Real impact. Control actual physical systems contributing to breakthroughs in cancer detection, materials science, and more Join a company backed by significant venture funding and a $42M government research programme
Apply now for immediate consideration!
A company building AI systems that can interact with the physical world at scale - designing experiments, controlling hardware, and accelerating scientific discovery from days to reality are looking for a Senior Firmware Engineer to join their team.
What Will I Be Doing
Design auto-generation flows transforming specs into deterministic firmware/RTL, including register maps, FSMs, and memory-mapped interfaces Own digital design correctness: clock/reset domains, CDC, timing constraints, and synthesis-aware RTL for FPGA/ASIC workflows Build integration layers for standard protocols (UART, SPI, I2C, CAN, Ethernet) and internal buses (AXI, APB, Wishbone) Develop verification infrastructure: self-checking testbenches, SVA, linting, coverage-driven regression, and formal methods Create tool-driven feedback loops running synthesis/simulation/formal verification with automatic fix proposals Ship CI/CD systems with golden tests, build determinism, and strict change controls Implement safety guardrails: invariants, privilege boundaries, audit logging, and policies preventing unsafe outputs Collaborate with platform, ML/agent, and domain teams to integrate into live hardware workflows
What We're Looking For
Strong digital design: FSM design, register maps, timing/constraints, CDC, hardware debug Hardware protocol integration and memory-mapped control patterns Verification skills: testbenches, SVA/assertions, UVM concepts, simulation tools (Verilator, commercial) FPGA/ASIC flow knowledge and ability to deliver synthesizable, timing-clean RTL Experience building reproducible automation pipelines: deterministic codegen, error parsing, CI/CD AI-powered code generation pipeline experience: spec
structured IR, templating, tool-calling loops, safety mechanisms Strong software engineering: clean architecture, testing, versioning, reliability mindset
What's In It For Me:
Salary of $200,000 - $300,000 dependent on experience Greenfield work. Build something that doesn't exist, at the frontier of physical AI and automated hardware design Real impact. Control actual physical systems contributing to breakthroughs in cancer detection, materials science, and more Join a company backed by significant venture funding and a $42M government research programme
Apply now for immediate consideration!