Quest Global
Design Verification Engineer
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Design Verification Engineer
role at
Quest Global .
Company Overview Quest Global delivers world‑class end‑to‑end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals, we are able to solve problems better, faster. This multi‑dimensional approach enables us to solve the most critical and large‑scale challenges across the aerospace & defense, automotive, energy, hi‑tech, healthcare, medical devices, rail and semiconductor industries.
Job Overview We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible and innovators, who are not only inspired by technology and innovation but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers.
What Will You Do
Design analog front‑end circuits, ADCs/DACs, comparators, and charge‑domain memory circuits supporting 4–8b MACs per cell.
Model and simulate analog/mixed‑signal circuits for noise, reliability, mismatch, and variation‑aware robustness under workload stress.
Develop and verify mixed‑signal interfaces between analog compute arrays and digital controllers, including timing and calibration logic.
Implement fault correction schemes such as ECC, BIST, and redundancy logic for multi‑bit precision memory‑CIM arrays.
Integrate analog circuits into digital layout flow, ensuring compatibility across multiple voltage and clock domains.
Collaborate with digital design teams on interface definitions and with layout teams for floorplan, power grid, and isolation strategies.
Contribute to tapeout execution: DRC/LVS signoff, corner simulation, test mode planning, and silicon debug hooks.
What You Will Bring
8+ years of production‑level analog/mixed‑signal IC design, including experience in embedded memory, compute‑in‑memory, or high‑precision sensor front ends.
Deep expertise in ADC/DAC design (SAR, pipelined, current‑steering) and analog compute blocks (capacitive MACs, charge integrators).
Strong understanding of multi‑voltage and multi‑clock domain integration, including domain isolation, level shifting, and interface timing closure.
Demonstrated experience in analog/digital co‑design with mixed‑signal floorplanning and layout coordination.
Familiarity with ECC, redundancy logic, and self‑test/BIST for analog memory arrays.
Tools: Cadence Virtuoso, Spectre, Verilog‑AMS, Synopsys CustomSim, Calibre, mixed‑signal simulation environments.
Experience with advanced process nodes including 22 nm/18 nm FDSOI and 12 nm FinFET is a strong plus.
Pay Range $160,000 - $180,000 a year
Benefits
401(k)
Dental insurance
Health insurance
Life insurance
Paid time off
Referral program
Vision insurance
Short/Long Term Disability
Work Requirements This role is considered an on‑site position located in
Palo Alto, CA . No travel is required.
Job Type Full‑time
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Design Verification Engineer
role at
Quest Global .
Company Overview Quest Global delivers world‑class end‑to‑end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals, we are able to solve problems better, faster. This multi‑dimensional approach enables us to solve the most critical and large‑scale challenges across the aerospace & defense, automotive, energy, hi‑tech, healthcare, medical devices, rail and semiconductor industries.
Job Overview We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible and innovators, who are not only inspired by technology and innovation but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers.
What Will You Do
Design analog front‑end circuits, ADCs/DACs, comparators, and charge‑domain memory circuits supporting 4–8b MACs per cell.
Model and simulate analog/mixed‑signal circuits for noise, reliability, mismatch, and variation‑aware robustness under workload stress.
Develop and verify mixed‑signal interfaces between analog compute arrays and digital controllers, including timing and calibration logic.
Implement fault correction schemes such as ECC, BIST, and redundancy logic for multi‑bit precision memory‑CIM arrays.
Integrate analog circuits into digital layout flow, ensuring compatibility across multiple voltage and clock domains.
Collaborate with digital design teams on interface definitions and with layout teams for floorplan, power grid, and isolation strategies.
Contribute to tapeout execution: DRC/LVS signoff, corner simulation, test mode planning, and silicon debug hooks.
What You Will Bring
8+ years of production‑level analog/mixed‑signal IC design, including experience in embedded memory, compute‑in‑memory, or high‑precision sensor front ends.
Deep expertise in ADC/DAC design (SAR, pipelined, current‑steering) and analog compute blocks (capacitive MACs, charge integrators).
Strong understanding of multi‑voltage and multi‑clock domain integration, including domain isolation, level shifting, and interface timing closure.
Demonstrated experience in analog/digital co‑design with mixed‑signal floorplanning and layout coordination.
Familiarity with ECC, redundancy logic, and self‑test/BIST for analog memory arrays.
Tools: Cadence Virtuoso, Spectre, Verilog‑AMS, Synopsys CustomSim, Calibre, mixed‑signal simulation environments.
Experience with advanced process nodes including 22 nm/18 nm FDSOI and 12 nm FinFET is a strong plus.
Pay Range $160,000 - $180,000 a year
Benefits
401(k)
Dental insurance
Health insurance
Life insurance
Paid time off
Referral program
Vision insurance
Short/Long Term Disability
Work Requirements This role is considered an on‑site position located in
Palo Alto, CA . No travel is required.
Job Type Full‑time
#J-18808-Ljbffr