Berkeley Square - Talent Specialists in IT & Engineering
Senior Hardware Design Engineer (Low Latency)
Berkeley Square - Talent Specialists in IT & Engineering, New York, New York, us, 10261
Senior Hardware Design Engineer (Low Latency)
Base pay range
$200,000.00/yr - $350,000.00/yr
Overview A leading global technology firm is looking for an
FPGA / ASIC Hardware Engineer
to design and build
high-performance, low-latency compute systems
used in real-time decision‑making environments. The role sits within a highly collaborative hardware team working on everything from
custom RTL designs to advanced compute and acceleration platforms .
You’ll be involved in architecting and implementing complex systems in
SystemVerilog , optimising data pipelines, and exploring new hardware technologies. The role is technical, hands‑on, and focused on performance, efficiency, and robustness rather than domain knowledge —
no industry‑specific background is required .
Key responsibilities
Design and develop FPGA and/or ASIC solutions as part of a cross‑functional engineering team
Implement and optimise RTL for complex data structures and processing pipelines
Explore and evaluate new tools, technologies, and architectures
Contribute to a fast‑moving, modern hardware development environment
Key requirements
2+ years’ experience in FPGA or ASIC RTL design
Deep understanding of FPGA/ASIC architectures and low‑level hardware behaviour
Experience with networking, data pipelines, or hardware acceleration (ML a plus)
Working knowledge of
Python and/or C++
Comfortable in a Linux environment with strong verification skills
Degree in Electrical Engineering, Computer Science, or related field
Seniority level Mid‑Senior level
Employment type Full‑time
Industries Financial Services, Banking, and Computers and Electronics Manufacturing
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Overview A leading global technology firm is looking for an
FPGA / ASIC Hardware Engineer
to design and build
high-performance, low-latency compute systems
used in real-time decision‑making environments. The role sits within a highly collaborative hardware team working on everything from
custom RTL designs to advanced compute and acceleration platforms .
You’ll be involved in architecting and implementing complex systems in
SystemVerilog , optimising data pipelines, and exploring new hardware technologies. The role is technical, hands‑on, and focused on performance, efficiency, and robustness rather than domain knowledge —
no industry‑specific background is required .
Key responsibilities
Design and develop FPGA and/or ASIC solutions as part of a cross‑functional engineering team
Implement and optimise RTL for complex data structures and processing pipelines
Explore and evaluate new tools, technologies, and architectures
Contribute to a fast‑moving, modern hardware development environment
Key requirements
2+ years’ experience in FPGA or ASIC RTL design
Deep understanding of FPGA/ASIC architectures and low‑level hardware behaviour
Experience with networking, data pipelines, or hardware acceleration (ML a plus)
Working knowledge of
Python and/or C++
Comfortable in a Linux environment with strong verification skills
Degree in Electrical Engineering, Computer Science, or related field
Seniority level Mid‑Senior level
Employment type Full‑time
Industries Financial Services, Banking, and Computers and Electronics Manufacturing
#J-18808-Ljbffr