Senior FPGA/ASIC Engineer - Low-Latency Compute

An innovative technology firm is seeking a Senior Hardware Design Engineer for designing and building high-performance, low-latency compute systems. This role involves architecting and implementing complex systems in SystemVerilog while collaborating in a dynamic hardware team. Ideal candidates will have 2+ years of FPGA or ASIC design experience, strong skills in Python or C++, and a degree in Electrical Engineering. A competitive salary range of $200,000 to $350,000 annually is offered. #J-18808-Ljbffr