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Staff/Sr. Staff Analog Design Engineer
ZipRecruiter - San Jose, California, United States, 95199
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Overview
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Overview
Job DescriptionJob DescriptionSalary: $160,000 to $175,000
Role
Credo is seeking a Staff Analog Design Engineer to join the R&D team. The Staff/Sr. Staff Analog Design Engineer will play a pivotal role in our integrated circuit development team, focusing on high-speed SerDes (Serializer/Deserializer) technology. This position requires an experienced professional who can drive complex analog circuit design from concept through production with minimal supervision. The ideal candidate will demonstrate both technical depth and leadership in designing high-performance analog circuits that meet stringent performance requirements for next- communication interfaces.
Responsibilities
Lead circuit design form initial concept and specifications
Execute comprehensive circuit simulations using CAD tools
Provide guidance to layout engineers throughout the physical design process and run post-layout simulations for verification
Conduct bench testing and debugging in laboratory environments
Basic Qualifications
MS in Electrical Engineering with 5+ years of experience or PhD in Electrical Engineering with 3+ years of experience
Proficient design experience in SerDes circuit blocks including: SAR-ADC, Phase interpolators, CTLE, Low jitter PLLs, high-speed clock distribution networks
Working knowledge of common SerDes standards and their electrical requirements
Experience with CAD tools for circuit simulation, layout, and physical verification
Strong understanding of analog layouts in FinFET processes and their impact on high-speed design
Skills
Experience with common analog circuit blocks (bias, bandgap, voltage regulators)
Excellent problem-solving abilities and analytical thinking
Strong teamwork and collaborative approach
Role
Credo is seeking a Staff Analog Design Engineer to join the R&D team. The Staff/Sr. Staff Analog Design Engineer will play a pivotal role in our integrated circuit development team, focusing on high-speed SerDes (Serializer/Deserializer) technology. This position requires an experienced professional who can drive complex analog circuit design from concept through production with minimal supervision. The ideal candidate will demonstrate both technical depth and leadership in designing high-performance analog circuits that meet stringent performance requirements for next- communication interfaces.
Responsibilities
Lead circuit design form initial concept and specifications
Execute comprehensive circuit simulations using CAD tools
Provide guidance to layout engineers throughout the physical design process and run post-layout simulations for verification
Conduct bench testing and debugging in laboratory environments
Basic Qualifications
MS in Electrical Engineering with 5+ years of experience or PhD in Electrical Engineering with 3+ years of experience
Proficient design experience in SerDes circuit blocks including: SAR-ADC, Phase interpolators, CTLE, Low jitter PLLs, high-speed clock distribution networks
Working knowledge of common SerDes standards and their electrical requirements
Experience with CAD tools for circuit simulation, layout, and physical verification
Strong understanding of analog layouts in FinFET processes and their impact on high-speed design
Skills
Experience with common analog circuit blocks (bias, bandgap, voltage regulators)
Excellent problem-solving abilities and analytical thinking
Strong teamwork and collaborative approach