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Design Verification Engineer
Kasmo Global - Milpitas 6 days ago
Title: Design Verification Engineer Austin, TX / Sunnyvale, CA Onsite Contract to Hire Responsibi...
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Design Verification Engineer
Kasmo Global - San Francisco 6 days ago
Title : Design Verification Engineer Location : San Jose, C s a Design Verification Engineer, you will c...
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US_East | Network Design Engineer_L3
Softpath System - Chicago 1 days ago
Possible 3 Month CTH | No Fees | Do Not Re-Post| ConfidentialTMR ID: # Z8TSS2Role: Design Verification EngineerWork location: Santa Cla...
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Principal SOC Verification Engineer
Synopsys, Inc. - Plano, Texas, us, 75086 3 days ago
We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, ...
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US_East | Network Design Engineer_L3
Expedite Technology Solutions LLC - Chicago 1 days ago
Possible 3 Month CTH | No Fees | Do Not Re-Post| Confidential TMR ID: # Z8TSS2 Role: Design Verification Engineer Work location: Santa ...
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ASIC Engineer, Design Verification
META - Sunnyvale, California, United States, 94087 4 days ago
Summary:Make your application after reading the following skill and qualification requirements for this position.
Meta is hiring ASIC Design...
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ASIC Engineer, Design Verification
META - Menlo Park, California, United States, 94025 5 days ago
Summary:Make your application after reading the following skill and qualification requirements for this position.
Meta is hiring ASIC Design...
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UVM/ SystemVerilog Design Verification Engineer
US Tech Solutions - Goleta, California, United States, 93117 5 days ago
Job TitleJob Description: The project relates to the design and verification of a custom controller for analog components. The controller ha...
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Principal SOC Verification Engineer
Synopsys, Inc. - Sunnyvale 11 hours ago
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era...
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Go to next pageTitle: Design Verification Engineer Austin, TX / Sunnyvale, CA Onsite Contract to Hire Responsibilities - Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
- Develop functional tests based on verification test plan
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
- Debug, root-cause, and resolve functional failures in the design, partnering with the Design team
- Collaborate with cross-functional teams like Design, Model, Emulation, and Silicon validation teams towards ensuring the highest design quality
Minimum Qualifications - B.S or M.S degree in Electrical Engineering, Computer Engineering or Computer Science
- Hands-on experience in Verilog, SystemVerilog, C/C++ based verification, and UVM methodology
- Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
- Experience in EDA tools and scripting (Python, Perl, Shell) used to build tools and flows for verification environments.
- Experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycle
Preferred Qualifications - Experience in the development of UVM based verification environments from scratch
- Experience with Design verification of Data-center applications like Video, AI/ML, and Networking designs
- Experience with revision control systems like Mercurial(Hg), Git or SVN
- Experience with verification of ARM/RISC-V based sub-systems or SoCs
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Design Verification Engineer
