Digital Design Engineer
Meta Platforms - Sunnyvale, California, United States, 94086
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Overview
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Overview
Reality Labs (RL) focuses on delivering Meta's vision through Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. Reality Labs Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR & VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms. We are growing our Machine Learning Asic Design and Architecture team within RL and are seeking engineers at all levels who will work with a world-class group of researchers and engineers using your digital design skills to implement and contribute to the development and optimization of low power machine learning accelerators and state-of-the-art SoCs. Digital Design Engineer Responsibilities
Contribute to Asic digital Architecture and design for low-power machine learning hardware accelerator Assist performance/power analysis of the design and help meet the power and performance targets Work with architects to map Machine learning algorithms on the hardware Support hand-off and integration of blocks into larger SOC environments Work across disciplines, brainstorm big ideas, build new methodologies Minimum Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 6+ years of experience as a Hardware Design Engineer for production silicon shipped in volume Experience in digital design Architecture, RTL coding Experience in Machine Learning IPs Silicon development Experience with at least 1 procedural programming language (C, C++, Python etc.) Preferred Qualifications
Experience in SoC integration and ASIC architecture Knowledge of Physical Design and Low power implementation Experience with Machine learning models, algorithms or accelerator architecture $142,000/year to $203,000/year + bonus + equity + benefits Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta. Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice here. Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form.