TPI Global Solutions
Overview
Resource Executive at TPI Global Solutions. 8 months contract Job Duties
This is a position for senior level RTL design engineer. As a part of the design team, candidate will be exposed to several IPs including Gbit SERDES, UCIe, PCIe I/F & high frequency design. Successful candidates will be participating in the DFX RTL coding/integration of leading edge I/O SoC in 3 nm processes. DFX RTL Design Engineer responsibilities include: Implementation of SOC DFT features (TAP controller, GPIOs, ESD structures, etc.) into RTL using Verilog/SystemVerilog, responsible for all RTL checks including lint/elab/CDC/RDC with 0-waivers, SOC level JTAG/IJTAG implementation (RTL/ICL/PDL), Gate level simulation using Synopsys VCS and Verdi, SOC-level SDC development and hand-off to PD, UPF development and hand-off to PD, Spyglass bring-up and analysis for scan readiness/test coverage gaps. Engagement in silicon bring-up and debug as needed. Education
Candidate must have a BS in EE or CS. MS is a plus. Seniority level
Mid-Senior level Employment type
Contract Job function
Other Industries
Semiconductor Manufacturing
#J-18808-Ljbffr
Resource Executive at TPI Global Solutions. 8 months contract Job Duties
This is a position for senior level RTL design engineer. As a part of the design team, candidate will be exposed to several IPs including Gbit SERDES, UCIe, PCIe I/F & high frequency design. Successful candidates will be participating in the DFX RTL coding/integration of leading edge I/O SoC in 3 nm processes. DFX RTL Design Engineer responsibilities include: Implementation of SOC DFT features (TAP controller, GPIOs, ESD structures, etc.) into RTL using Verilog/SystemVerilog, responsible for all RTL checks including lint/elab/CDC/RDC with 0-waivers, SOC level JTAG/IJTAG implementation (RTL/ICL/PDL), Gate level simulation using Synopsys VCS and Verdi, SOC-level SDC development and hand-off to PD, UPF development and hand-off to PD, Spyglass bring-up and analysis for scan readiness/test coverage gaps. Engagement in silicon bring-up and debug as needed. Education
Candidate must have a BS in EE or CS. MS is a plus. Seniority level
Mid-Senior level Employment type
Contract Job function
Other Industries
Semiconductor Manufacturing
#J-18808-Ljbffr