VIVA USA INC
Overview
DFX RTL Design Engineer – Hybrid. Senior level RTL design engineer role exposed to multiple IPs including Gbit SERDES, UCIe, PCIe I/F & high frequency design. Involves DFX RTL coding/integration for leading-edge I/O SoC in 3 nm processes. Responsibilities
Implementation of SOC DFT features (TAP controller, GPIOs, ESD structures, etc.) into RTL using Verilog/SystemVerilog, including RTL checks (lint/elab/CDC/RDC) with 0-waivers. SOC-level JTAG/IJTAG implementation (RTL/ICL/PDL). Gate-level simulation using Synopsys VCS and Verdi. SOC-level SDC development and hand-off to PD. UPF development and hand-off to PD. Spyglass bring-up and analysis for scan readiness/test coverage gaps. Participation in silicon bring-up and debug as needed. Qualifications
Education: BS in Electrical Engineering or Computer Science. MS is a plus. Mandatory skills: RTL checks, RTL coding, RTL implementation Gbit SERDES, UCIe, PCIe I/F DFX RTL coding, DFX RTL integration RTL checks (lint, elab, CDC, RDC), I/O SoC SOC DFT features (TAP controller, GPIO, ESD structures) Verilog, SystemVerilog Spyglass, Spyglass bring-up, Spyglass analysis VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical, mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era, recently separated veteran, Active war time or campaign badge veteran, Armed forces service medal veteran, or disabled veteran. Please contact us at for any complaints, comments and suggestions. Contact Details: Account co-ordinator: Godwin D Antony Raj VIVA USA INC. 3601 Algonquin Road, Suite 425 Rolling Meadows, IL 60008
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DFX RTL Design Engineer – Hybrid. Senior level RTL design engineer role exposed to multiple IPs including Gbit SERDES, UCIe, PCIe I/F & high frequency design. Involves DFX RTL coding/integration for leading-edge I/O SoC in 3 nm processes. Responsibilities
Implementation of SOC DFT features (TAP controller, GPIOs, ESD structures, etc.) into RTL using Verilog/SystemVerilog, including RTL checks (lint/elab/CDC/RDC) with 0-waivers. SOC-level JTAG/IJTAG implementation (RTL/ICL/PDL). Gate-level simulation using Synopsys VCS and Verdi. SOC-level SDC development and hand-off to PD. UPF development and hand-off to PD. Spyglass bring-up and analysis for scan readiness/test coverage gaps. Participation in silicon bring-up and debug as needed. Qualifications
Education: BS in Electrical Engineering or Computer Science. MS is a plus. Mandatory skills: RTL checks, RTL coding, RTL implementation Gbit SERDES, UCIe, PCIe I/F DFX RTL coding, DFX RTL integration RTL checks (lint, elab, CDC, RDC), I/O SoC SOC DFT features (TAP controller, GPIO, ESD structures) Verilog, SystemVerilog Spyglass, Spyglass bring-up, Spyglass analysis VIVA USA is an equal opportunity employer and is committed to maintaining a professional working environment that is free from discrimination and unlawful harassment. The Management, contractors, and staff of VIVA USA shall respect others without regard to race, sex, religion, age, color, creed, national or ethnic origin, physical, mental or sensory disability, marital status, sexual orientation, or status as a Vietnam-era, recently separated veteran, Active war time or campaign badge veteran, Armed forces service medal veteran, or disabled veteran. Please contact us at for any complaints, comments and suggestions. Contact Details: Account co-ordinator: Godwin D Antony Raj VIVA USA INC. 3601 Algonquin Road, Suite 425 Rolling Meadows, IL 60008
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