TPI Global Solutions
Senior Digital Design Engineer
TPI Global Solutions, San Francisco, California, United States, 94199
Overview
Direct message the job poster from TPI Global Solutions Talent
Talent Acquisition Professional, Hiring Candidates for Semiconductor & Automotive Domain (DV, PD, RTL, ASIC, FPGA, PCB,Layout,Storage,Firmware,Device… Duration:
12+ months Responsibilities
This is a position for senior level RTL design engineer. As a part of the design team, candidate will be exposed to several IPs including Gbit SERDES, UCIe, PCIe I/F & high frequency design. Successful candidates will be participating in the DFX RTL coding/integration of leading edge I/O SoC in 3 nm processes. This DFX RTL Design Engineer is expected to contribute in : Implementation of SOC DFT features (TAP controller, GPIOs, ESD structures etc) into RTL using Verilog/system verilog, responsible for all RTL checks including lint/elab/CDC/RDC with 0-waivers, SOC level JTAG/IJTAG implementation (RTL/ICL/PDL), Gate level simulation using Synopsys VCS and Verdi, SOC-level SDC development and hand-off to PD, UPF development and hand-off to PD, Spyglass bringup and analysis for scan readiness/test coverage gaps. Candidate will also be engaged in silicon bring-up and debug as needed. Seniority level
Mid-Senior level Employment type
Contract Job function
Information Technology Industries Industries
Semiconductor Manufacturing and Computers and Electronics Manufacturing
#J-18808-Ljbffr
Direct message the job poster from TPI Global Solutions Talent
Talent Acquisition Professional, Hiring Candidates for Semiconductor & Automotive Domain (DV, PD, RTL, ASIC, FPGA, PCB,Layout,Storage,Firmware,Device… Duration:
12+ months Responsibilities
This is a position for senior level RTL design engineer. As a part of the design team, candidate will be exposed to several IPs including Gbit SERDES, UCIe, PCIe I/F & high frequency design. Successful candidates will be participating in the DFX RTL coding/integration of leading edge I/O SoC in 3 nm processes. This DFX RTL Design Engineer is expected to contribute in : Implementation of SOC DFT features (TAP controller, GPIOs, ESD structures etc) into RTL using Verilog/system verilog, responsible for all RTL checks including lint/elab/CDC/RDC with 0-waivers, SOC level JTAG/IJTAG implementation (RTL/ICL/PDL), Gate level simulation using Synopsys VCS and Verdi, SOC-level SDC development and hand-off to PD, UPF development and hand-off to PD, Spyglass bringup and analysis for scan readiness/test coverage gaps. Candidate will also be engaged in silicon bring-up and debug as needed. Seniority level
Mid-Senior level Employment type
Contract Job function
Information Technology Industries Industries
Semiconductor Manufacturing and Computers and Electronics Manufacturing
#J-18808-Ljbffr