LanceSoft, Inc.
Overview
This range is provided by LanceSoft, Inc.. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
Base pay range $60.00/hr - $71.00/hr
Position Manager ( USA and Canada Staffing / Recruitment ) - Semiconductor / VLSI / EDA / Embedded
Job Title
- RTL DFX/DFT Design Engineer (Combination work experience of RTL Design and DFT)
Job Location
- San Jose-CA or Onsite/Hybrid or Fully remote also for right candidate
Job Description-
This is a position for senior level RTL design engineer. As a part of the design team, candidate will be exposed to several IPs including Gbit SERDES, UCIe, PCIe I/F & high frequency design. Successful candidates will be participating in the DFX RTL coding/integration of leading edge I/O SoC in 3 nm processes.
This
DFX RTL Design Engineer
is expected to contribute in :
Implementation of SOC DFT features (TAP controller, GPIOs, ESD structures etc) into RTL using Verilog/system verilog, responsible for all RTL checks including lint/elab/CDC/RDC with 0-waivers, SOC level JTAG/IJTAG implementation (RTL/ICL/PDL), Gate level simulation using Synopsys VCS and Verdi, SOC-level SDC development and hand-off to PD, UPF development and hand-off to PD, Spyglass bringup and analysis for scan readiness/test coverage gaps. Candidate will also be engaged in silicon bring-up and debug as needed.
Candidate must have a
BS in EE or CS. MS
is a plus.
Seniority Mid-Senior level
Employment type Contract
Job function Industries: Semiconductor Manufacturing
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Base pay range $60.00/hr - $71.00/hr
Position Manager ( USA and Canada Staffing / Recruitment ) - Semiconductor / VLSI / EDA / Embedded
Job Title
- RTL DFX/DFT Design Engineer (Combination work experience of RTL Design and DFT)
Job Location
- San Jose-CA or Onsite/Hybrid or Fully remote also for right candidate
Job Description-
This is a position for senior level RTL design engineer. As a part of the design team, candidate will be exposed to several IPs including Gbit SERDES, UCIe, PCIe I/F & high frequency design. Successful candidates will be participating in the DFX RTL coding/integration of leading edge I/O SoC in 3 nm processes.
This
DFX RTL Design Engineer
is expected to contribute in :
Implementation of SOC DFT features (TAP controller, GPIOs, ESD structures etc) into RTL using Verilog/system verilog, responsible for all RTL checks including lint/elab/CDC/RDC with 0-waivers, SOC level JTAG/IJTAG implementation (RTL/ICL/PDL), Gate level simulation using Synopsys VCS and Verdi, SOC-level SDC development and hand-off to PD, UPF development and hand-off to PD, Spyglass bringup and analysis for scan readiness/test coverage gaps. Candidate will also be engaged in silicon bring-up and debug as needed.
Candidate must have a
BS in EE or CS. MS
is a plus.
Seniority Mid-Senior level
Employment type Contract
Job function Industries: Semiconductor Manufacturing
#J-18808-Ljbffr