Mixed-Signal Verification Engineer: SystemVerilog & SPICE

A technology company is seeking a Mixed Signal Model Verification Engineer for a hybrid role in San Jose, CA. The ideal candidate should have extensive experience in modeling mixed signal circuits in SystemVerilog, a strong understanding of HDL/SPICE co-simulations, and proficiency in RTL design languages. Responsibilities include verifying behavioral models, writing constraints for CAD tools, and debugging mismatches between models and circuit behaviors. This position offers competitive compensation and a dynamic working environment. #J-18808-Ljbffr