Onsite Mixed-Signal Verification Engineer (SystemVerilog)

A leading tech company in Santa Clara, CA is seeking a Mixed Signal Model Verification Engineer for a 1-year project. The role involves verifying behavioral models in SystemVerilog, debugging mixed signal circuits, and ensuring equivalence with circuit designs. Candidates should have extensive experience in mixed signal modeling, a solid grasp of HDL/SPICE co-simulations, and proficiency in analog circuit design. This is an on-site, W2 position offering a great opportunity in a vibrant work environment. #J-18808-Ljbffr