CyberCoders
Principal SoC Frontend Design Engineer
CyberCoders, San Jose, California, United States, 95199
Principal SoC Frontend Design Engineer
Job Title:
Principal SoC Frontend Design Engineer Job Location:
San Jose, CA Compensation:
$170K - $230K base plus stock options
Position Overview We’re looking for a Sr. Staff or Principal SoC Frontend Design Engineer to lead RTL design, synthesis, and timing analysis for our cutting‑edge interconnect SoCs. This role is central to building the silicon backbone of our switch architecture, enabling scalable memory pooling and high‑bandwidth AI workloads.
Key Responsibilities
Lead the front‑end design of SoC projects, ensuring high‑quality RTL design and implementation.
Develop and optimize SDC constraints for timing closure across complex clocking domains.
Perform static timing analysis using PrimeTime, ensuring robust timing across process corners.
Collaborate with architecture, verification, and back‑end teams to deliver production‑quality silicon.
Integrate and validate PHY interfaces for PCIe, DDR, and Ethernet, supporting hybrid interconnect standards.
Contribute to technical reviews, sign‑off flows, and continuous improvement of design methodologies.
Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
7+ years of experience in SoC design and front‑end design roles.
Proficient in RTL design and Verilog/SystemVerilog for synthesizable logic.
Strong command of SDC constraint development and static timing analysis techniques.
Expertise in Synopsys tools: Design Compiler, PrimeTime.
Familiarity with design and implementation of PHY interfaces such as PCIe, Ethernet, DDR.
Benefits: PTO/Vacation days, equity offered.
Other Details
Seniority level:
Not applicable
Employment type:
Full‑time
Job function:
Information Technology
Industries:
Staffing and Recruiting
#J-18808-Ljbffr
Principal SoC Frontend Design Engineer Job Location:
San Jose, CA Compensation:
$170K - $230K base plus stock options
Position Overview We’re looking for a Sr. Staff or Principal SoC Frontend Design Engineer to lead RTL design, synthesis, and timing analysis for our cutting‑edge interconnect SoCs. This role is central to building the silicon backbone of our switch architecture, enabling scalable memory pooling and high‑bandwidth AI workloads.
Key Responsibilities
Lead the front‑end design of SoC projects, ensuring high‑quality RTL design and implementation.
Develop and optimize SDC constraints for timing closure across complex clocking domains.
Perform static timing analysis using PrimeTime, ensuring robust timing across process corners.
Collaborate with architecture, verification, and back‑end teams to deliver production‑quality silicon.
Integrate and validate PHY interfaces for PCIe, DDR, and Ethernet, supporting hybrid interconnect standards.
Contribute to technical reviews, sign‑off flows, and continuous improvement of design methodologies.
Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
7+ years of experience in SoC design and front‑end design roles.
Proficient in RTL design and Verilog/SystemVerilog for synthesizable logic.
Strong command of SDC constraint development and static timing analysis techniques.
Expertise in Synopsys tools: Design Compiler, PrimeTime.
Familiarity with design and implementation of PHY interfaces such as PCIe, Ethernet, DDR.
Benefits: PTO/Vacation days, equity offered.
Other Details
Seniority level:
Not applicable
Employment type:
Full‑time
Job function:
Information Technology
Industries:
Staffing and Recruiting
#J-18808-Ljbffr