Lead SoC Frontend RTL Engineer - Equity & High-Performance AI

A technology staffing agency is seeking a Principal SoC Frontend Design Engineer in San Jose, CA. This role involves leading RTL design, performing static timing analysis, and ensuring high-quality silicon production. Candidates should have 7+ years of SoC design experience and be proficient in Verilog/SystemVerilog. Competitive compensation between $170K and $230K plus stock options is offered, along with additional benefits such as PTO and equity. #J-18808-Ljbffr