Senior Design Verification Engineer - DDR5/Memory IP (Remote, PST)

A global staffing firm is seeking a Design Verification Engineer in Santa Clara, CA. This hybrid position requires a minimum of 8 years of design verification experience, along with strong skills in System Verilog and UVM. The ideal candidate is self-motivated, possesses excellent communication skills, and has a solid background in collaborating with teams across time zones. Responsibilities include developing tests for verification and supporting functional coverage verification. Join this innovative team and contribute to industry-leading technologies. #J-18808-Ljbffr