Senior ASIC Verification Engineer | SystemVerilog/UVM Expert

A leading technology firm in San Jose is seeking a Design Verification Engineer to develop advanced verification environments and methodologies. The role demands 12+ years of experience in ASIC verification, strong knowledge of System Verilog, and excellent communication skills. You will collaborate with design and verification teams to meet high-performance design requirements and analyze complex verification challenges. The company offers a competitive salary and comprehensive benefits package. #J-18808-Ljbffr