Precision Resources Company, Inc.
ASIC Design Engineer Remote work is possible
Precision Resources Company, Inc. - Harrisburg, Pennsylvania, us, 17124
Work at Precision Resources Company, Inc.
Overview
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Overview
ASIC Design for Test Engineer
Work Location: PA Telecommuting or Baltimore, Mooresville, NC Duration: 12 Months + 9/80 Work Schedule
Description Looking for a DFT (Design for Test) engineer to join our highly qualified, diverse individuals as part of our ASIC design team.
Responsibilities: • Responsible for DFT (Design for Testability) aspects of ASIC Design thorough understanding of digital design concepts • Adhering to Northrop Grumman ASIC development process. • Knowledgeable in VHDL, Verilog or System Verilog RTL coding and highly proficient in DFT methodologies. • Responsible for operating in a team environment and collaborating across the different teams as required to accomplish the goals.
Basic Qualifications Bachelor's degree in Electrical or Computer Engineering with 8+ years' experience. (or a Master's degree with 6 years of experience) • U.S. Citizenship is required • Experience in full product life cycle of ASIC Design • Experience with Cadence and/or Mentor test insertion and ATPG tools • Experience with hierarchical scan testing, IEEE-1500 and/or IEEE-1687, test compression, JTAG IEEE-1149.1 and IEEE-1149.6 (AC JTAG) • Experience with memory BIST and logic BIST • Experience generating test patterns and analyzing and debugging test failures • Experience working with test engineers to implement ATPG vectors on tester hardware • Proficiency in HDL (VHDL/Verilog/System Verilog) and scripting languages such as Tcl, Python or Perl • Effective communication and presentation skills and high proficiency in technical problem solving
Preferred Qualifications: • Master's Degree in Electrical or Computer Engineering • Expertise of using Cadence Modus DFT tools • Knowledge of Synthesis, P&R and Static Timing Analysis would be a plus
Additional Job details: Working with the team of ASIC engineers to develop DFT architecture and its implementation into a complex ASIC. The size of the group this position will be supporting is 15+ Technical environment: Design using Linux platforms Multi disciplined team of Digital design, Verification and Physical Implementation engineers, many of whom will be working from different sites across USA. Daily tasks: Develop DFT architecture, provide detailed documentation and work with wider Digital designers to drive the implementation. Need someone with prior experience. The DFT expert can ramp up quickly, work with Cadence Application engineers as needed to solve issues as they arise.
Work Location: PA Telecommuting or Baltimore, Mooresville, NC Duration: 12 Months + 9/80 Work Schedule
Description Looking for a DFT (Design for Test) engineer to join our highly qualified, diverse individuals as part of our ASIC design team.
Responsibilities: • Responsible for DFT (Design for Testability) aspects of ASIC Design thorough understanding of digital design concepts • Adhering to Northrop Grumman ASIC development process. • Knowledgeable in VHDL, Verilog or System Verilog RTL coding and highly proficient in DFT methodologies. • Responsible for operating in a team environment and collaborating across the different teams as required to accomplish the goals.
Basic Qualifications Bachelor's degree in Electrical or Computer Engineering with 8+ years' experience. (or a Master's degree with 6 years of experience) • U.S. Citizenship is required • Experience in full product life cycle of ASIC Design • Experience with Cadence and/or Mentor test insertion and ATPG tools • Experience with hierarchical scan testing, IEEE-1500 and/or IEEE-1687, test compression, JTAG IEEE-1149.1 and IEEE-1149.6 (AC JTAG) • Experience with memory BIST and logic BIST • Experience generating test patterns and analyzing and debugging test failures • Experience working with test engineers to implement ATPG vectors on tester hardware • Proficiency in HDL (VHDL/Verilog/System Verilog) and scripting languages such as Tcl, Python or Perl • Effective communication and presentation skills and high proficiency in technical problem solving
Preferred Qualifications: • Master's Degree in Electrical or Computer Engineering • Expertise of using Cadence Modus DFT tools • Knowledge of Synthesis, P&R and Static Timing Analysis would be a plus
Additional Job details: Working with the team of ASIC engineers to develop DFT architecture and its implementation into a complex ASIC. The size of the group this position will be supporting is 15+ Technical environment: Design using Linux platforms Multi disciplined team of Digital design, Verification and Physical Implementation engineers, many of whom will be working from different sites across USA. Daily tasks: Develop DFT architecture, provide detailed documentation and work with wider Digital designers to drive the implementation. Need someone with prior experience. The DFT expert can ramp up quickly, work with Cadence Application engineers as needed to solve issues as they arise.