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Dice is the leading career destination for tech experts at every stage of their careers. Our client, Skywaves MP LLC, is seeking an RTL Architect – SERDES. Apply via Dice today!
Position RTL Architect – SERDES
Location USA (Onsite/Hybrid) Austin, TX & Santa Clara, CA
Experience Required 8+ years
Notice Period Immediate
Key Responsibilities
Define and own the RTL architecture for high-speed and many‑lane SERDES IPs.
Lead RTL design, coding, and integration of SERDES blocks.
Collaborate with analog, verification, PD, and validation teams to ensure seamless integration and successful silicon bring‑up.
Drive micro‑architecture development, specification reviews, and design documentation.
Perform lint, CDC, and synthesis checks to ensure design quality.
Support post‑silicon validation and debug efforts.
Mentor junior engineers and provide technical leadership in design reviews.
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering or a related field.
8+ years of experience in RTL design/architecture, with direct hands‑on expertise in SERDES design (PAM4/NRZ, PCIe, Ethernet, CXL, etc.).
Strong understanding of high‑speed serial interfaces, clocking, and data‑path architecture.
Proficiency in Verilog/SystemVerilog for RTL coding.
Proficiency in modelling with MATLAB.
Solid knowledge of ASIC design flow, including synthesis, STA, and physical design considerations.
Knowledge of simulation and verification methodologies (UVM, assertions, coverage).
Strong analytical/debugging skills and ability to work cross‑functionally.
Preferred Skills
Experience with advanced process nodes.
Familiarity with DFT, low‑power design techniques, and ECO flows.
Exposure to system‑level architecture for networking, HPC, or data‑center applications.
Strong communication and leadership skills.
Seniority Level Mid‑Senior level
Employment Type Full‑time
Job Function Engineering and Information Technology
Industries Software Development
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Position RTL Architect – SERDES
Location USA (Onsite/Hybrid) Austin, TX & Santa Clara, CA
Experience Required 8+ years
Notice Period Immediate
Key Responsibilities
Define and own the RTL architecture for high-speed and many‑lane SERDES IPs.
Lead RTL design, coding, and integration of SERDES blocks.
Collaborate with analog, verification, PD, and validation teams to ensure seamless integration and successful silicon bring‑up.
Drive micro‑architecture development, specification reviews, and design documentation.
Perform lint, CDC, and synthesis checks to ensure design quality.
Support post‑silicon validation and debug efforts.
Mentor junior engineers and provide technical leadership in design reviews.
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering or a related field.
8+ years of experience in RTL design/architecture, with direct hands‑on expertise in SERDES design (PAM4/NRZ, PCIe, Ethernet, CXL, etc.).
Strong understanding of high‑speed serial interfaces, clocking, and data‑path architecture.
Proficiency in Verilog/SystemVerilog for RTL coding.
Proficiency in modelling with MATLAB.
Solid knowledge of ASIC design flow, including synthesis, STA, and physical design considerations.
Knowledge of simulation and verification methodologies (UVM, assertions, coverage).
Strong analytical/debugging skills and ability to work cross‑functionally.
Preferred Skills
Experience with advanced process nodes.
Familiarity with DFT, low‑power design techniques, and ECO flows.
Exposure to system‑level architecture for networking, HPC, or data‑center applications.
Strong communication and leadership skills.
Seniority Level Mid‑Senior level
Employment Type Full‑time
Job Function Engineering and Information Technology
Industries Software Development
Referrals increase your chances of interviewing at Jobs via Dice by 2x.
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